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The etch-back process may be performed using a RIE or a chemical-mechanical planarization (CMP) process. The second layer of material may be planarized using an etch-back process in which the second layer of material and any mask material used to pattern the second layer of material are removed. As the second layer of material is formed, it will grow over the contacts and gate structures. After the RIE has been performed, the polysilicon may be removed, leaving the contacts and gate structures in the active regions.Īfter the contacts and gate structures have been formed, a second layer of material may be formed over the substrate and the contacts and gate structures. This layer may then be selectively etched by a known etching process such as a reactive-ion etching (RIE). Typically, the active regions and contacts are formed in a layer of material such as polysilicon. One common type of masking and etching involves defining active regions in a substrate, and defining contacts and gate structures on the active regions. Once the desired pattern has been transferred, the photoresist is removed and the substrate may be etched using the patterned mask as an etching mask. One such technique includes using a mask material such as photoresist on the substrate and patterning the mask material such that the desired pattern can be transferred to the substrate. Electrical connections may then be made to the source, drain, and back gates of the transistor using conductive contacts formed in one or more interlayer dielectric layers and electrically conductive structures formed in one or more of the dielectric layers.įeatures in the substrate may be formed using known masking and etching techniques. Once the features have been formed, a transistor may be defined by gate structures and active regions in the substrate. For example, the circuit devices may be formed by defining features such as gate electrodes in the substrate.
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